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PIC18F85J11 FAMILY

DS39774D-page 170

2010 Microchip Technology Inc.

16.1

CCP Module Configuration

Each Capture/Compare/PWM module is associated

with a control register (generically, CCPxCON) and a

data register (CCPRx). The data register, in turn, is

comprised of two 8-bit registers: CCPRxL (low byte)

and CCPRxH (high byte). All registers are both

readable and writable.

16.1.1

CCP MODULES AND TIMER

RESOURCES

The CCP modules utilize Timers 1, 2 or 3, depending

on the mode selected. Timer1 and Timer3 are available

to modules in Capture or Compare mode, while Timer2

is available for modules in PWM mode.

TABLE 16-1:

CCPx MODE – TIMER

RESOURCE

The assignment of a particular timer to a module is

determined by the timer to CCPx enable bits in the

T3CON register (Register 15-1). Both modules may be

active at any given time and may share the same timer

resource if they are configured to operate in the same

mode (Capture/Compare or PWM) at the same time.

The interactions between the two modules are

summarized in Table 16-2.

Depending on the configuration selected, up to four

timers may be active at once, with modules in the same

configuration (Capture/Compare or PWM) sharing

timer resources. The possible configurations are

shown in Figure 16-1.

16.1.2

OPEN-DRAIN OUTPUT OPTION

When operating in Output mode (i.e., in Compare or

PWM modes), the drivers for the CCPx pins can be

optionally configured as open-drain outputs. This

feature allows the voltage level on the pin to be pulled

to a higher level through an external pull-up resistor

and allows the output to communicate with external

circuits without the need for additional level shifters.

The open-drain output option is controlled by the

CCP2OD and CCP1OD bits (TRISG<6:5>). Setting the

appropriate bit configures the pin for the corresponding

module for open-drain operation.

16.1.3

CCP2 PIN ASSIGNMENT

The pin assignment for CCP2 (Capture input, Compare

and PWM output) can change, based on device config-

uration. The CCP2MX Configuration bit determines

which pin CCP2 is multiplexed to. By default, it is

assigned to RC1 (CCP2MX = 1). If the Configuration bit

is cleared, CCP2 is multiplexed with RE7.

Changing the pin assignment of CCP2 does not

automatically change any requirements for configuring

the port pin. Users must always verify that the appropri-

ate TRIS register is configured correctly for CCP2

operation, regardless of where it is located.

FIGURE 16-1:

CCPx AND TIMER INTERCONNECT CONFIGURATIONS

CCPx Mode

Timer Resource

Capture

Compare

PWM

Timer1 or Timer3

Timer2

TMR1

TMR2

TMR3

CCP2

CCP1

TMR1

TMR2

TMR3

CCP2

CCP1

TMR1

TMR3

TMR2

CCP2

CCP1

T3CCP<2:1> = 00

T3CCP<2:1> = 01

T3CCP<2:1> = 1x

Timer1 is used for all Capture

and Compare operations for

all CCP modules. Timer2 is

used for PWM operations for

all CCP modules. Modules

may

either

timer

resource as a common time

base.

Timer1 is used for Capture

and Compare operations for

CCP1 and Timer 3 is used for

CCP2.

Both the modules use Timer2

as a common time base if they

are in PWM modes.

Timer3 is used for all Capture

and Compare operations for

all CCP modules. Timer2 is

used for PWM operations for

all CCP modules. Modules

may

either

timer

resource as a common time

base.

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